Illinois Scan Architecture Design

Testing of present day VLSI circuits with standard linear scan procedures using the Built-In Self Test (BIST) takes a significant amount of time, with the sheer number of sequential elements running into tens of thousands. Using the Illinois Scan Architecture, we propose to significantly reduce the test application time, by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scanin input. Experimental results for ISCAS89 circuits show significant reduction in test application time, with a minor reduction in test coverage.